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| Integrated Circuit Systems, Inc. Product Brief M2004-02 Series * FREQUENCY TRANSLATION PLL SERIES PIN ASSIGNMENT (9 x 9 mm SMT) M0 GND REF_CLK DIF_REF nDIF_REF REF_SEL NC NC VCC M1 M2 M3 M4 M5 VCC DNC DNC DNC 27 26 25 24 23 22 21 20 19 GENERAL DESCRIPTION The M2004-02 and its variants are VCSO (Voltage Controlled SAW Oscillator) based clock generator PLLs designed for clock frequency translation and jitter attenuation in a high-speed data communications system. The clock multiplication ratio and output divider ratio are pin selectable. External loop components allow the tailoring of PLL loop response. Variants of the device add the features Hitless Switching with Phase Build-out (HS/PBO) to ensure that reference clock reselection does not disrupt the output clock. A fixed Narrow Loop Bandwidth feature (Fixed NBW) is included in the some of the device variants. 28 29 30 31 32 33 34 35 36 M2004-X2 (Top View) 18 17 16 15 14 13 12 11 10 NC MR nFOUT FOUT GND N1 N0 VCC GND FEATURES * Ideal for OC-48/192 data clock * Integrated SAW (surface acoustic wave) delay line * VCSO frequency from 300 to 700MHz ** * Low phase jitter of < 0.5ps rms, typical (12kHz to 20MHz or 50kHz to 80MHz) * Pin-selectable configuration * Hitless Switching with Phase Build-out (HS/PBO) added to all but the M2004-02 to ensure SONET/SDH MTIE and TDEV compliance during reference clock reselection * Fixed Narrow Loop Bandwidth feature (Fixed NBW) added to some of the product variants (see Table 2) * Reference clock inputs support differential LVDS, LVPECL, as well as single-ended LVCMOS, LVTTL * Industrial temperature available * Single 3.3V power supply * Small 9 x 9 mm SMT (surface mount) package GND GND GND OP_IN nOP_OUT nVC VC OP_OUT nOP_IN Figure 1: Pin Assignment Example Input / Output Frequency Combinations Input (MHz) VCSO ** (MHz) Output (MHz) 19.44 77.76 622.08 77.76 311.04 155.52 622.08 Application OC-12 / 48 /192 Table 1: Example Input / Output Frequency Combinations Device Variants and Corresponding Functions Hitless Switching / Phase Build-out Triggered by Phase Transient Mux Reselection M2004-02 no no M2004-12 Yes Yes M2004-22 no no M2004-32 Yes Yes M2004-42 no Yes M2004-52 no Yes Variant Fixed NBW no no Yes Yes no Yes Table 2: Device Variants and Corresponding Functions * Series of parts numbered M2004-02, -12, -22, -32, -42, and -52. ** Specify VCSO center frequency at time of order. SIMPLIFIED BLOCK DIAGRAM M2004-X2 DIF_REF nDIF_REF REF_CLK REF_SEL M Divider N Divider 6 M5:0 2 N1:0 FOUT nFOUT 0 1 Loop Filter VCSO Figure 2: Simplified Block Diagram M2004-02 Series PB Rev 1.2 M2004-02 Series Frequency Translation PLL Series 1 2 3 4 5 6 7 8 9 MR Revised 10Sep2003 Integrated Circuit Systems, Inc. Communications Modules w w w. i c s t . c o m tel (508) 852-5400 |
Price & Availability of M2004-X2
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